Diagnosing Scan Chain Faults via Image Comparison; Classifying Common Scan Chain Fault Types
Source: VLSI Test Principles and Architectures
Comparing the snapshot image against the observed image isolates stuck-at defects within a scan chain. This differential analysis pinpoints exactly where signal propagation fails during shift operations, enabling precise fault localization without exhaustive logic simulation. The expected snapshot registers (1, 1, 0, 0) across q1 through q4, but the observed output reads all zeros. A stuck-at-0 fault between q2 and q3 forces downstream flops to zero while corrupting the upstream capture. This mismatch confirms the defect location, demonstrating how image comparison transforms raw scan data into actionable diagnostic evidence for VLSI test architectures.
Scan chain diagnosis relies on structured fault models to distinguish failure mechanisms. These faults are classified by two independent characteristics: functional versus timing behavior, and permanent versus intermittent occurrence. Intermittent faults manifest nondeterministically under specific operating conditions like power supply noise. Functional failures primarily involve stuck-at and bridging defects. Timing violations target flip-flop constraints, separating setup-time and hold-time breaches. Setup violations stem from late input signals and further subdivide into slow-to-rise and slow-to-fall faults, reflecting asymmetric logic cell driving strengths. Hold violations result from premature output transitions. This taxonomy enables precise syndrome classification during flush tests, guiding targeted diagnostic strategies for silicon debug.
Distinct output signatures isolate specific flip-flop defects within a serial test path. Applying a uniform scan-in pattern reveals whether a cell is permanently latched or merely timing-degraded, enabling precise hardware fault localization without full circuit simulation. Shifting the rightmost bit first, a stuck-at-0 defect forces the entire observed syndrome to zero, while stuck-at-1 yields all ones. Transition delays manifest as periodic bit failures matching the input sequence; slow-to-rise corrupts rising edges, and slow-to-fall distorts falling transitions. Underlined bits mark exact failure points, directly mapping electrical defects to logical positions for targeted repair.