Transformation of Gated Clock Structures; Transformation of Gated Clock for Test Generation
Source: VLSI Test Principles and Architectures
Gated clock structures obstruct automatic test pattern generation by blocking scan shifting and fault propagation. Transforming these conditional enable networks into standard synchronous logic resolves the controllability bottleneck. The schematic demonstrates two common gating topologies converted into equivalent multiplexer-based registers. An AND gate merging the system Clock with enable signal b becomes a mux selecting between the feedback path and data input a, driven by a free-running Clock. Similarly, a flop triggered directly by enable b is restructured using the same selection logic. This normalization preserves functional behavior while ensuring full scan accessibility during manufacturing test.
Handling multi-clock designs requires collapsing independent timing domains into a single test clock to enable efficient automatic test pattern generation (ATPG). This transformation replaces separate flip-flop triggers with a unified control signal, simplifying sequential logic verification. The schematic demonstrates merging Clock1 and Clock2 through a combinational function f to drive both registers simultaneously. While one-hot clocking maximizes fault coverage, it risks generating excessively large test sets. Conversely, staggered clocking yields slightly lower coverage but permits combinational ATPG via circuit expansion. Sequential ATPG remains viable for these transformed structures, though it typically incurs longer execution times compared to combinational approaches.