Mixing Edge-Triggered Scan Cells; Cross-Clock-Domain Scan with Lock-Up Latch
Source: VLSI Test Principles and Architectures
Scan replacement substitutes original storage elements with functionally equivalent scan cells, creating a scan-ready design optimized for power, speed, and area. Mixing negative-edge and positive-edge triggered cells within a single chain is permissible but introduces specific timing dependencies that must be managed during synthesis. The circuit structure shows SC1 capturing on the falling clock edge while SC2 captures on the rising edge. Consequently, data launched from X requires a full clock cycle to propagate to Y, as evidenced by the one-cycle delay between the D1 blocks in the timing diagram. This half-cycle offset prevents race conditions between adjacent cells but effectively halves the shift frequency compared to a uniform edge-triggered chain.
Scan replacement substitutes original storage with functionally equivalent scan cells, but crossing asynchronous clock domains risks data corruption during shift operations. Inserting a lock-up latch between domains stabilizes the signal path against clock skew and phase misalignment. The circuit structure places a negative-edge latch between scan cells SCp and SCq, driven by CK1 and CK2 respectively. Timing waveforms confirm that intermediate node Y holds data D1, D2, and D3 steady during CK2 transitions, preventing race conditions at the destination flop. This structural addition ensures reliable test pattern shifting across independent clock domains without violating setup or hold constraints, preserving scan chain integrity in multi-clock designs.