RTL Scan Synthesis: Generated Clock Repair

Generated clocks derived from register outputs violate scan design rules because downstream flops lack a stable, controllable test clock. RTL scan synthesis resolves this by inserting equivalent RTL structures rather than library cells, preserving functional behavior while enabling testability. Schematic (b) shows the violation: the second flip-flop is clocked directly by clk_15, a divided signal from the first register. The repair in (d) inserts a multiplexer controlled by test mode TM. During normal operation, clk_15 drives the flop; during test, the primary clk is selected via clk_test. This guarantees a clean, controllable clock for scan shifting without altering the RTL's functional intent.