Conceptual View of Test Generation; Stuck-at Fault Model in Logic Circuits
Source: VLSI Test Principles and Architectures
Test generation fundamentally relies on distinguishing faulty silicon from a known-good reference by applying identical stimuli and comparing responses. This conceptual model establishes the baseline for automatic test pattern generation (ATPG) algorithms in VLSI design. Identical inputs drive parallel defect-free and defective circuit models, with the physical flaw marked as X. Their respective outputs feed an exclusive-OR gate. The engineering objective is to compute a specific input vector that forces a logic 1 at this comparator. A high output confirms a behavioral divergence, successfully detecting the targeted fault. This mechanism transforms physical manufacturing defects into observable digital mismatches, enabling systematic yield screening and quality assurance.
Stuck-at fault modeling isolates permanent logic defects by forcing a specific node to a fixed binary value, decoupling it from upstream gate behavior. Detecting this defect requires propagating a conflicting signal from primary inputs to the faulty site, creating a measurable divergence between the good and defective circuit responses at the output. The schematic illustrates node d locked at logic 1, overriding the OR gate's computed result. To expose this error, test vectors must drive inputs a and b such that the fault-free path yields logic 0 at d. Since the AND gate combines this forced high with input c, the discrepancy propagates to terminal e only when c is asserted. This activation and propagation sequence forms the foundation of automatic test pattern generation for combinational logic.