SDC No Masking on False Paths; SDC False Path Hold Time X-Propagation
Source: Tessent Scan and ATPG User’s Manual v2025.4
Static timing analysis exceptions only suppress paths that remain logically inactive; when a declared false path carries no transition, it cannot mask valid sensitization elsewhere. This preserves test coverage for the genuine logic cone. The SDC command constrains the route from clk1 through G3/A, yet the dotted false path stays static at 111 during cycle-1. Because no glitch propagates along that branch, the true paths through the intersection cone drive U3/D unimpeded. The waveform confirms U3/Q captures the correct value without interference. Consequently, applying this exception introduces no masking risk, validating that unreachable paths safely bypass timing checks while leaving functional propagation intact.
Hold-time exceptions on false paths directly corrupt the active clock edge, injecting unknown states into downstream logic. Unlike setup constraints that govern future cycles, this exception forces immediate X-propagation through the intersection cone, degrading test coverage and functional predictability. The SDC command targets clk1 through G3/A, masking the true path from U1. Consequently, G1/Q resolves to X, which propagates through G3 and G4 into U3/Q. The waveform confirms U3/D and U3/Q transitioning to unknowns during cycle-1. This demonstrates how improperly scoped false-path declarations inadvertently poison hold-check windows, requiring precise pin-level constraints to preserve deterministic timing analysis.
SDC false path setup exceptions suppress timing checks but propagate unknown logic states into downstream sequential elements. Declaring a path false removes the setup constraint, yet the destination flop still captures indeterminate values on the subsequent clock edge, degrading test coverage and simulation fidelity. The command targets the path from ck1 through G3/A, defining an intersection cone at G1 and an effect cone extending to U3. Because the setup check is waived, U3/D and U3/Q resolve to X-states during cycle-2. This demonstrates that setup exceptions impact the following clock edge, forcing unknowns into the effect cone rather than guaranteeing valid data capture.
Applying a two-cycle setup exception relaxes timing closure by shifting the capture requirement, but it fundamentally alters test observability. The constraint forces the automatic test pattern generation engine to treat intermediate logic states as don't-cares, directly impacting fault coverage metrics for the affected cone. The waveform evidence confirms that masking occurs during the second cycle, where U3/D holds an undefined value while ck2 remains inactive. Signal propagation through the intersection cone only becomes stable after the second cycle completes. Consequently, any stuck-at or transition faults residing within this specific multicycle window evade detection unless the ATPG tool explicitly models the extended path delay.