Fixing Bidirectional I/O Ports; Fixing Gated Clocks for Testability
Source: VLSI Test Principles and Architectures
Okay, let's take this gently—before we look at the specific circuit diagrams, I want to make sure we're all on the same page about *why* we're changing these designs. We aren't just adding gates for fun; we are fixing structural obstacles that stop our test equipment from doing its job. See this bit? The first hurdle is bidirectional ports. If you have an input and output sharing a line, they can fight each other during a scan shift—that's bus contention. We fix this by gating the output buffer with the Scan Enable signal, ensuring only one side drives the line when it matters. Next up are gated and derived clocks. These signals are tricky because they might not toggle when we expect them to, or they come from internal sources we can't control directly. To keep things moving, we add bypass mechanisms—like OR gates or multiplexers—to force the clock path open during testing. Then there are feedback loops. If combinational logic feeds back into itself, it can oscillate or hold random values. That makes fault detection nearly impossible. We break these loops using a Test Mode signal to insert scan points, effectively cutting the cycle so we can observe what's happening inside. Does that click? Each of these fixes serves one master goal: enabling reliable scan shift and capture. Without these structural changes, our test vectors would be meaningless noise. Nice—keep going. As we move through the figures, remember that every added gate or mux is a deliberate choice to trade a little complexity for massive gains in test coverage. You've got this part.
Gated clocks save power, but they quietly block scan shifting unless we force the path open during test. That is the whole reason this fix exists. See circuit (a)? The latch feeds CEN into the AND gate, so a low enable simply starves GCK and the DFF never toggles. Hmm, that traps us. Circuit (b) slips an OR gate in front of the latch, letting TM or SE pull CEN high on demand. Oh, that's clean. Pick TM and coverage drops because the gating logic stays masked; pick SE and you keep capture visibility at the cost of harder test generation. Does that tradeoff click?
Okay, let's take this gently. The core issue here is bus contention during scan shifts. In the original circuit on the left, the flip-flop output Q drives the I/O line directly through the buffer. If that line is already being driven externally while we shift test data, we get a conflict. Does that click? Now look at the modified version on the right. See that AND gate? It sits between Q and the output buffer, controlled by an inverted SE signal. When Scan Enable is active, the gate forces the output low, effectively disconnecting the internal driver from the shared I/O pin. Oh—that's clean. This simple gating prevents the fight without breaking the functional path when SE is inactive. Nice—keep going.
Okay, let's take this gently. A derived clock like ICK is generated internally, so we cannot control it directly from the outside during a scan test. That leaves the logic it drives effectively hidden from our test patterns. See circuit (a)? The feedback flip-flop creates ICK, which then clocks DFF1 and DFF2 directly. Hmm, that internal generation is exactly the trap. Nice, the fix is clean. In circuit (b), a multiplexer sits between the source and the loads. When the test mode signal TM is high, the mux selects CK, a clock we fully control from a primary input. This bypasses the derived path entirely for the whole test operation. Does that click? We simply swap in a controllable clock so every flip-flop stays reachable.