Fixing Bidirectional I/O Ports; Fixing Gated Clocks for Testability
Source: VLSI Test Principles and Architectures
Derived clocks generated internally from storage elements lack direct primary-input controllability, creating significant obstacles during scan-based testing. To ensure comprehensive fault coverage, these internal timing signals must be effectively bypassed or gated throughout the entire test operation. The original circuit directly couples the flip-flop output to the bidirectional buffer, allowing an uncontrolled derived clock to inadvertently drive the I/O pin during scan shifts. The modified architecture inserts an AND gate controlled by the inverted Scan Enable (SE) signal. This gating mechanism forces the output driver inactive whenever SE is asserted, successfully isolating the derived clock path and preventing bus contention while preserving normal functional behavior.
Gated clocks create derived clock signals that are not directly controllable from primary inputs, blocking fault propagation during scan testing. The original circuit in (a) generates GCK by ANDing the global CK with a latched enable CEN, making the downstream DFF unreachable when gating logic disables the clock. The modified circuit in (b) inserts an OR gate before the latch, driven by a test mode signal TM or SE. Asserting this signal forces the enable high, bypassing the gating logic and restoring direct CK control to the DFF throughout the test operation. This structural fix ensures derived clocks remain observable and controllable without altering functional behavior.
Derived clocks generated internally from storage elements lack direct controllability from primary inputs, creating significant barriers for structural testing. To ensure complete observability and controllability of downstream logic, these internal signals must be bypassed during test operations. The original circuit routes a divided clock ICK directly to flip-flops DFF1 and DFF2, isolating them from external test vectors. The modified design inserts a multiplexer controlled by test mode TM. When TM equals one, the mux selects the primary clock CK, overriding the internal divider. This bypass restores direct external control over the clock tree, enabling standard scan-based testing without altering functional behavior during normal operation.