X-Bounding Methods in BIST-Ready Cores; Scan-Based X-Bounding for Unknown Source Blocking
Source: VLSI Test Principles and Architectures
Analog block outputs, such as those from analog-to-digital converters (ADCs), often exhibit unknown X states during Built-In Self-Test (BIST). These indeterminate values propagate through downstream logic and corrupt test responses, so every X source must be forced to a known value before evaluation. Five bounding techniques address this: static 0-control and 1-control points gate the signal with BIST_mode, while bypass logic, control-only scan points, and full scan points use multiplexers or flip-flops to substitute deterministic data. The document recommends bypass logic and scan-point insertion over simple control points because they preserve observability and yield higher fault coverage during structural testing.
Non-scan storage elements like D flip-flops require dedicated test structures to ensure Built-In Self-Test (BIST) controllability without corrupting functional states. Adding specific clock points for asynchronous set/reset circuitry prevents unknown X-values from propagating during scan operations, yielding higher fault coverage than simple bypass logic. The schematic integrates a NOR gate driven by SRCK and SE to gate the reset input R independently of the functional clock CK. When SE activates, the multiplexer selects Scan-In over Functional Logic, while the gated SRCK signal forces a known state at R. This architecture isolates test initialization from critical timing paths, ensuring stored data remains intact throughout BIST sequences while maintaining full observability of the storage element.