Automatic Repair of Generated Clock Violations in RTL Scan Synthesis

Generated clock violations compromise scan testability when derived clocks directly drive storage elements without test-mode controllability. Automatic repair at the RTL level resolves this by inserting a multiplexer to switch between functional and test clock domains. Panel (b) shows the violation where clk_15 directly clocks the destination flip-flop. Panel (d) demonstrates the repair: a mux controlled by TM selects clk_test during scan operations, ensuring proper shift-register behavior while preserving functional timing via clk_15 in normal mode. This RTL-level insertion maintains design equivalence while enabling complete scan chain stitching for advanced DFT structures.