Setup and Hold Time Exception Paths; Across Clock Domain Hold Time Exception
Source: Tessent Scan and ATPG User’s Manual v2025.4
Setup and hold time exceptions define critical timing violation paths where data transitions fail to meet flip-flop capture requirements relative to the clock edge. These violations directly compromise test response integrity during structural testing. The waveform shows data0 transitioning across the Clk2 rising clock event at U3. A setup time exception occurs when data changes too close before this edge, specifically impacting at-speed test patterns. Conversely, a hold time exception happens when data shifts immediately after the edge, affecting any test pattern and typically arising across different clock domains. Identifying these windows is essential for accurate Static Timing Analysis (STA) and ensuring reliable silicon validation.
Simultaneous clock pulsing across domains creates false paths that trigger hold time exceptions between asynchronous flip-flops. This timing violation risks data corruption when launch and capture clocks overlap unexpectedly during test patterns. Pulsing Clk1 and Clk2 together drives a rising transition at U1's output, sensitizing the path through G1 to U3. If Clk2 arrives late at the destination flop, the new logic zero captures instead of the previous one. Such across-clock-domain hold failures require SDC constraints to mark these paths as false or multicycle, preventing static timing analysis from flagging unreachable violations.
A non-specific false path declaration propagates the timing exception across an entire effect cone rather than isolating a single route. Issuing a broad command like add_false_paths -from U3 forces the tool to treat every downstream logic path originating from that register as false, which risks masking valid timing violations in unrelated circuitry. The shaded region traces this propagation from the U3 output through combinational gates G2, G4, and G7 to sink register U6, while simultaneously branching upward through G3 and G6 toward U5. Because the constraint lacks a specific destination endpoint, the exception bleeds into multiple fanout branches. Precise SDC definitions must pair source and destination nodes to prevent this over-constraining behavior and preserve accurate static timing analysis coverage.