Breaking Combinational Feedback for Scan Shift; Fixing Asynchronous Reset Signals in Scan Chains
Source: VLSI Test Principles and Architectures
Sequentially controlled asynchronous set and reset signals derived from internal combinational feedback can block proper scan chain shifting. These signals must be forced inactive during shift operations to guarantee reliable test data movement. The original circuit contains a direct feedback loop through the combinational logic. The modified design inserts a multiplexer controlled by the test mode signal TM. When TM is asserted, the flip-flop output Q feeds the logic input instead of the state signal S, effectively breaking the feedback path. While this ensures shift integrity, relying solely on TM prevents fault detection within the asynchronous control logic. Substituting the scan enable signal SE allows these internal faults to be captured during normal operation.
Sequentially controlled asynchronous resets block proper scan shifting unless forced inactive during test. The original circuit drives the active-low reset of SFF2 directly from SFF1, leaving the chain vulnerable to unintended clearing mid-shift. The modified design inserts an OR gate tied to test mode TM. Asserting TM permanently disables RL throughout testing, guaranteeing clean data capture. However, this masking prevents fault detection within the reset logic itself. Substituting the scan enable SE for TM restores observability during capture cycles, balancing shift reliability against comprehensive structural test coverage.